Due to the maturity of the communication market, the application of the relevant IC also persistently grows. With the prevalence of portable electronic products, such as mobile phones, battery runtime becomes very important. Thus, how to promote the efficiency and stability of batteries has been a challenge in the related field.
Because of compactness, low noise and high conversion efficiency, the LDO (Low Dropout) linear voltage regulator has been the mainstream of small-power regulators and step-down transformers and has been widely used in portable electronic products and communication-related products.
In the existing products/methods, three stages of amplifiers are usually adopted to increase the gain of an LDO linear voltage regulator and achieve a higher accuracy. However, such an approach is apt to result in the instability of the LDO linear voltage regulator. Therefore, various frequency compensation methods are proposed to stabilize the system. A pole-zero compensation, i.e., adding an external big-size capacitor to lower the dominant pole and increase phase margin, was proposed, wherein a big-size output capacitor is needed to move the dominant pole to low frequency to maintain stability. As the dominant pole is located at the output of LDO linear voltage regulator, the maximum load current will influence the stability. Such a method has the following disadvantages:                1. As the dominant pole is located at the output of LDO linear voltage regulator, such a circuit needs a bigger capacitor to stabilize the system. However, it is hard to integrate on a single chip, which increases difficulty in system-on-chip.        2. Generally speaking, a greater gain, which can promote system accuracy, is expected. However, increasing gain will decrease system stability in such a circuit. Therefore, a compromise must be made between gain and stability.        3. Greater load current means lower load resistance and greater dominant pole. The greater the dominant pole, the poorer the system stability. Thus, system stability limits load current in such a circuit.        
Refer to FIG. 1. Someone proposed an LDO linear voltage regulator using nested Miller compensation to solve the abovementioned problems. The LDO linear voltage regulator 10 comprises an input terminal VIN receiving input DC voltage; an output terminal VOUT outputting a stabilized output voltage; a first-stage amplifier 11; a second-stage amplifier 12 cascaded to the first-stage amplifier 11; and a power transistor 13 cascaded to the second-stage amplifier 12. The source of the power transistor 13 is coupled to the input terminal VIN, and the drain is coupled to the output terminal VOUT, and the gate is coupled to the output terminal of the second-stage amplifier 12. The anti-phase input terminal of the first-stage amplifier 11 receives a reference voltage signal input by a reference voltage generator 14, and the in-phase input terminal is coupled to a node 15, and the output terminal is coupled to the input terminal of the second-stage amplifier 12. A first Miller compensation capacitor Cm1 is arranged in the feedback path between the output terminal of the first-stage amplifier 11 and the drain of the power transistor 13. A second Miller compensation capacitor Cm2 is arranged in the feedback path between the output terminal of the second-stage amplifier 12 and the drain of the power transistor 13. A feedback resistor network 20 is arranged between the drain of the power transistor 13 and the in-phase input terminal of the first-stage amplifier 11. The feedback resistor network 20 has two resistors RF1 and RF2, which form a voltage divider. The node 15 is formed in between resistors RF1 and RF2, and the in-phase input terminal of the first-stage amplifier 11 is coupled to the node 15. The output terminal VOUT of the LDO linear voltage regulator 10 is coupled to an external output capacitor CL with a parasitic resistance RESR.
In the LDO linear voltage regulator 10 using nested Miller compensation, the dominant pole is moved to the output of the first-stage amplifier 11 via pole splitting. Such an approach does not need a big-size output capacitor CL. The system can still have superior stability under a zero-capacitance output capacitor CL, which benefits SOC (System-on-Chip) application, reduces circuit board area and decreases external elements.
Refer to FIG. 2 for a small-signal model of the abovementioned system. The small-signal model comprises a gain stage gm1Vs of the first-stage amplifier 11, a gain stage gm2V2 of the second-stage amplifier 12, and an output stage of the power transistor 13, and the resistors RF1 and RF2 form the feedback resistor network 20. gm1, gm2, gmp are respectively the transductions of the first-stage amplifier 11, the second-stage amplifier 12 and the output stage. RO1 and RO2 are respectively the output impedances of the first-stage amplifier 11 and the second-stage amplifier 12. CP1 and CP2 are respectively the parasitic capacitances of the first-stage amplifier 11 and the second-stage amplifier 12. COUT is the output capacitance, and RESR is the parasitic resistance of the output capacitor. Cm1 and Cm2 are respectively the first and second Miller compensation capacitances. ROUT(=RL∥ROp∥(RF1+RF1)) is the equivalent output resistance, wherein RL is the load resistance, and ROp is the output resistance of the power PMOS transistor.
From the small-signal model in FIG. 2, the system transformation equation is obtained:
                              L          ⁡                      (            s            )                          =                                                            A                0                            ⁡                              (                                  1                  -                                      s                    ⁢                                                                  C                                                  m                          ⁢                                                                                                          ⁢                          2                                                                                            g                        mp                                                                              -                                                            s                      2                                        ⁢                                                                                            C                                                      m                            ⁢                                                                                                                  ⁢                            1                                                                          ⁢                                                  C                                                      m                            ⁢                                                                                                                  ⁢                            2                                                                                                                                                g                                                      m                            ⁢                                                                                                                  ⁢                            2                                                                          ⁢                                                  g                          mp                                                                                                                    )                                      ⁢                          (                              1                +                                  s                                                            C                      OUT                                        ⁢                                          R                      ESR                                                                                  )                                                          (                              1                +                                  s                                      p                                                                  -                        3                                            ⁢                      dB                                                                                  )                        ⁡                          [                              1                +                                  s                  ⁡                                      (                                                                                            C                          OUT                                                ⁢                                                  R                          ESR                                                                    +                                                                        C                                                      m                            ⁢                                                                                                                  ⁢                            2                                                                                                    g                                                      m                            ⁢                                                                                                                  ⁢                            2                                                                                                                )                                                  +                                                      s                    2                                    ⁡                                      (                                                                                            C                                                      m                            ⁢                                                                                                                  ⁢                            2                                                                          ⁢                                                  C                          OUT                                                                                                                      g                                                      m                            ⁢                                                                                                                  ⁢                            2                                                                          ⁢                                                  g                          mp                                                                                      )                                                              ]                                                          (        1        )            wherein the DC loop gain is given by
                                          A            0                    =                                    g                              m                ⁢                                                                  ⁢                1                                      ⁢                          g                              m                ⁢                                                                  ⁢                2                                      ⁢                          g              mp                        ⁢                          R                              O                ⁢                                                                  ⁢                1                                      ⁢                          R                              O                ⁢                                                                  ⁢                2                                      ⁢                                          R                OUT                            ⁡                              (                                                      R                                          F                      ⁢                                                                                          ⁢                      2                                                                                                  R                                              F                        ⁢                                                                                                  ⁢                        1                                                              +                                          R                                              F                        ⁢                                                                                                  ⁢                        2                                                                                            )                                                    ,                            (        2        )            and the dominant pole
                              p                                    -              3                        ⁢                                                  ⁢            dB                          =                  1                                    C                              m                ⁢                                                                  ⁢                1                                      ⁢                          g                              m                ⁢                                                                  ⁢                2                                      ⁢                          g              mp                        ⁢                          R                              O                ⁢                                                                  ⁢                1                                      ⁢                          R                              O                ⁢                                                                  ⁢                2                                      ⁢                          R              OUT                                                          (        3        )            The damping factor can thus be worked out:
                    ζ        =                              1            2                    ⁢                      (                                                            C                  OUT                                ⁢                                  R                  ESR                                            +                                                C                                      m                    ⁢                                                                                  ⁢                    2                                                                    g                                      m                    ⁢                                                                                  ⁢                    2                                                                        )                    ⁢                                                                      g                                      m                    ⁢                                                                                  ⁢                    2                                                  ⁢                                  g                  mp                                                                              C                                      m                    ⁢                                                                                  ⁢                    2                                                  ⁢                                  C                  OUT                                                                                        (        4        )            
From the abovementioned equations, it is known: the damping factor ζ varies with the output capacitance COUT and the parasitic resistance RESR of the output capacitor. When the output capacitance COUT and the parasitic resistance RESR are very small, the second-stage transduction gm2 must be reduced so as to obtain a sufficiently high damping factor ζ and use a smaller Miller compensation capacitance Cm2. However, the system feedback gain will become smaller, and the system accuracy is decreased. Thus, a compromise must be made between the damping factor ζ and the system loop gain.